For the purpose of reducing power consumption, a gate circuit called a power gate circuit is disposed between a power supply and the ground to suppress a leak current from an unused circuit in a standby state by disconnect the circuit from the power supply through switch control.
FIG. 1 is a diagram showing a schematic exemplary configuration of a common power gate.
In the power gate circuit 1 shown in FIG. 1, a circuit 2 of interest is connected to a power supply potential VDD, and a power gate switch 3 constituted by an NMOS transistor is connected between an virtual ground VGND of the circuit 2 and the ground GND.
FIG. 1 shows an example of isolation of the circuit from the ground GND, and the power gate switch 3 may alternatively be inserted between the power supply VDD and the circuit 2 of interest.
When the circuit 2 is in a standby state, a leak current can flow and a standby current can increase if no power gate is provided. The circuit 2 is electrically isolated from the power supply and the ground GND to suppress a leak current by turning the power gate circuit off using a power gate control circuit 4 in the standby state.
FIG. 2 is a graph showing a model of a current that flows when the power supply of the power gate circuit in FIG. 1 is turned on.
When the power gate switch 3 is turned from off to on, a rush current flows as show in FIG. 2, and the current may exceed an upper limit for a current flowing through the circuit 2.
A known method of suppressing such a rush current is the use of a multi-stage power gate circuit having a multiplicity of power gate stages which are separately controlled (see JP-A-2008-300696 and JP-A-2008-34667 (Patent Documents 1 and 2)).
FIG. 3 is a diagram of a multi-stage power gate circuit.
FIG. 4 is a graph showing a model of a current that flows when the power supply of the multi-stage power gate circuit is turned on.
In order to suppress a rush current in the system shown in FIG. 1, power gate switches 3-1 to 3-3 are grouped into a multiplicity of stages (three stages in this case), and those stages are independently controlled by the power gate control circuit 4.
When timing control is exercised such that power gate circuits 3-1, 3-2, and 3-3 in such a system are sequentially turned on, a rush current is suppressed as shown in FIG. 4.